Partial Reconfiguration Bitstream Compression for Virtex FPGAs

An adaptive LZW algorithm for compressing partial bitstreams of Virtex FPGAs was presented. The adaptations of algorithm were based on analysis of the three-level data regularity of the configuration bitstreams. Partial bitstreams were created through Xilinx module-based partial reconfiguration flow. The experiment demonstrated down to 43.69% compression ratio for partial bitstreams of several real-world applications.