Title :
A 0.13 /spl mu/m DRAM technology for giga bit density stand-alone and embedded DRAMs
Author :
Kim, K.N. ; Chung, T.Y. ; Jeong, H.S. ; Moon, J.T. ; Park, Y.W. ; Jeong, G.T. ; Lee, K.H. ; Koh, G.H. ; Shin, D.W. ; Hwang, Y.S. ; Kwak, D.W. ; Uh, H.S. ; Ha, D.W. ; Lee, J.W. ; Shin, S.H. ; Lee, M.H. ; Chun, Y.S. ; Lee, J.K. ; Park, B.J. ; Oh, J.H. ; Lee
Author_Institution :
Technol. Dev. Memory Device Bus., Samsung Electron. Co., Yongin City, South Korea
Abstract :
In this paper, a 0.13 /spl mu/m DRAM technology is developed with KrF lithography. In order to extend KrF lithography to 0.13 /spl mu/m generation, full CMP technology is developed in order to provide flat surface. Full self-aligned contact (SAC) technology can make memory cell processes easy because memory cell landing pads and storage node contact plug can be formed with self-aligned manner respect to word-line and bit-line. By these technologies, the extremely small memory cell is easily realized without any yield loss. Low-temperature PAOCS MIS capacitor with Al/sub 2/O/sub 3/ can greatly reduce the aspect ratio of metal contact, thereby yielding stable metal contact process. And it can help DRAM technology easily to merge with logic process. The 0.13 /spl mu/m integration technology is successfully demonstrated with 1 Gb DRAM.
Keywords :
DRAM chips; MIS capacitors; chemical mechanical polishing; integrated circuit technology; ultraviolet lithography; 0.13 micron; 1 Gbit; Al/sub 2/O/sub 3/; CMP technology; DRAM technology; KrF lithography; embedded DRAM; low temperature PAOCS MIS capacitor; memory cell; self-aligned contact; stand-alone DRAM; Amorphous silicon; Capacitors; Etching; Lithography; Logic; Metallization; Moon; Random access memory; Silicon compounds; Temperature;
Conference_Titel :
VLSI Technology, 2000. Digest of Technical Papers. 2000 Symposium on
Conference_Location :
Honolulu, HI, USA
Print_ISBN :
0-7803-6305-1
DOI :
10.1109/VLSIT.2000.852748
