AS/400 64-bit powerPC-compatible processor implementation

Author

Borkenhagen, John M. ; Handlogten, Glen H. ; Irish, John D. ; Levenstein, Sheldon B.

Author_Institution

IBM Corp., Rochester, MN, USA

fYear

1994

fDate

10-12 Oct 1994

Firstpage

192

Lastpage

196

Abstract

An implementation of the 64-bit PowerPC Architecture optimized for the IBM AS/400 commercial environment is described. This 64-bit BiCMOS semicustom implementation runs at a clock rate of 170 MHz. The processor features a 4-way superscalar pipelined fixed point unit which can dispatch and execute up to 4 instructions each cycle, a floating point unit with a peak rate of 500 MFLOPs, 8-Kbyte L0 instruction cache, 256-Kbyte L1 cache, and support for 64-Gbyte of main storage. A 4-way rightly-coupled symmetric multi-processor system is one of several configurations supported by this implementation

Keywords

BiCMOS integrated circuits; buffer storage; digital arithmetic; microprocessor chips; 170 MHz; 256 kB; 4-way superscalar pipelined fixed point unit; 500 MFLOPS; 64 GB; 64 bit; 64-bit powerPC-compatible processor; 8 kB; AS/400; BiCMOS semicustom implementation; L0 instruction cache; L1 cache; clock rate; floating point unit; main storage; rightly-coupled symmetric multi-processor system; BiCMOS integrated circuits; Cache storage; Clocks; Flexible printed circuits; Laboratories; Multichip modules; Operating systems; Pipelines; Power system modeling; Registers;

fLanguage

English

Publisher

ieee

Conference_Titel

Computer Design: VLSI in Computers and Processors, 1994. ICCD '94. Proceedings., IEEE International Conference on

Conference_Location

Cambridge, MA

Print_ISBN

0-8186-6565-3

Type

conf

DOI

10.1109/ICCD.1994.331886

Filename

331886