Title :
Timing verification and optimization for the PowerPC processor family
Author :
Mains, Robert E. ; Mosher, Thomas A. ; Van Ginneken, Lukas P P P ; Damiano, Robert F.
Author_Institution :
RISC Syst., IBM Corp., Austin, TX, USA
Abstract :
This paper presents the timing verification and optimization tools used for the 601, 603, 604 and 620 PowerPC processor designs. The timing verification is done by static timing analysis at the chip level, while the timing optimization is done by synthesis at the macro level. A method for automatically deriving timing constraints for timing optimization is described
Keywords :
flip-flops; logic design; microprocessor chips; PowerPC processor family; optimization; static timing analysis; timing constraints; timing verification; Clocks; Constraint optimization; Control system synthesis; Delay effects; Latches; Logic design; Logic gates; Master-slave; Performance analysis; Timing;
Conference_Titel :
Computer Design: VLSI in Computers and Processors, 1994. ICCD '94. Proceedings., IEEE International Conference on
Conference_Location :
Cambridge, MA
Print_ISBN :
0-8186-6565-3
DOI :
10.1109/ICCD.1994.331929
