DocumentCode :
2161744
Title :
On retiming for FPGA logic module minimization
Author :
Chen, Y.P. ; Wong, D.F.
Author_Institution :
Dept. of Comput. Sci., Texas Univ., Austin, TX, USA
fYear :
1994
fDate :
10-12 Oct 1994
Firstpage :
394
Lastpage :
397
Abstract :
We consider the problem of minimizing the number of logic modules for Actel 2 or Actel 3 sequential circuits. We make use of the fact that if a flip-flop is the only destination of its driving combinational block, then both the flip-flop and the combinational block can be put in a sequential module. Retiming technique is applied to minimize the number of resistors that can not be merged with combinational blocks. We formulate the problem as an integer linear program. We show that the constraint matrix of the integer program is totally unimodular. As a result, we can solve our logic module minimization problem optimally by solving the linear relaxation of the integer program
Keywords :
integer programming; linear programming; logic arrays; minimisation of switching nets; sequential circuits; Actel 2; Actel 3 sequential circuits; FPGA logic module minimization; constraint matrix; flip-flop; integer linear program; logic module minimization; retiming; retiming technique; unimodular; Circuit synthesis; Field programmable gate arrays; Flip-flops; Logic circuits; Logic design; Logic functions; Minimization; Pulse inverters; Registers; Sequential circuits;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Computer Design: VLSI in Computers and Processors, 1994. ICCD '94. Proceedings., IEEE International Conference on
Conference_Location :
Cambridge, MA
Print_ISBN :
0-8186-6565-3
Type :
conf
DOI :
10.1109/ICCD.1994.331934
Filename :
331934
Link To Document :
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