Title :
0.18 um modular triple self-aligned embedded split-gate flash memory
Author :
Mih, R. ; Harrington, J. ; Houlihan, K. ; Hyun Koo Lee ; Chan, K. ; Johnson, J. ; Bomy Chen ; Jiang Yan ; Schmidt, A. ; Gruensfelder, C. ; Kisang Kim ; Shum, D. ; Lo, C. ; Lee, D. ; Levi, A. ; Chung Lam
Author_Institution :
Div. of Microelectron., IBM, Hopewell Junction, NY, USA
Abstract :
A split-gate flash memory cell has been embedded in a 0.18 um high performance CMOS logic process with copper interconnects. A novel triple self-aligned (SA3) process provides a compact cell and high degree of modularity. The entire memory cell structure is defined with one single mask in an area less than 13F/sup 2/. Source-side channel hot electron program and poly-poly tunneling erase enable low power consumption suitable for low voltage applications.
Keywords :
CMOS memory circuits; flash memories; low-power electronics; 0.18 micron; CMOS logic process; Cu; copper interconnect; embedded split-gate flash memory cell; low voltage operation; modular triple self-aligned process; poly-poly tunneling erase; source-side channel hot electron programming; CMOS logic circuits; CMOS technology; Channel hot electron injection; Copper; Etching; Flash memory; Low voltage; Microelectronics; Nonvolatile memory; Split gate flash memory cells;
Conference_Titel :
VLSI Technology, 2000. Digest of Technical Papers. 2000 Symposium on
Conference_Location :
Honolulu, HI, USA
Print_ISBN :
0-7803-6305-1
DOI :
10.1109/VLSIT.2000.852793
