A CMOS technology platform for 0.13 /spl mu/m generation SOC (system on a chip)

Author

Yoshimura, H. ; Nakayama, T. ; Nishigohri, M. ; Inohara, M. ; Miyashita, K. ; Morifuji, E. ; Oishi, A. ; Kawashima, H. ; Habu, M. ; Koike, H. ; Takato, H. ; Toyoshima, Y. ; Ishiuchi, H.

Author_Institution

Microelectron. Eng. Lab., Toshiba Corp., Yokohama, Japan

fYear

2000

fDate

13-15 June 2000

Firstpage

144

Lastpage

145

Abstract

In this paper, we demonstrate a platform technology for 0.13 /spl mu/m generation SOC (system on a chip). 0.11 /spl mu/m LOGIC process with trench capacitor DRAM cell of 0.3 /spl mu/m/sup 2/ and 6Tr SRAM cell of 2.5 /spl mu/m/sup 2/ is described. Source/drain extensions are formed after deep junction activation by using disposable gate sidewalls. Thus ideal annealing condition is applied to source/drain extensions for shallow junction formation. In addition, second sidewalls for Co salicide are optimized for suppression of boron penetration from p/sup +/ poly-silicon gate.

Keywords

CMOS digital integrated circuits; annealing; application specific integrated circuits; integrated circuit metallisation; isolation technology; random-access storage; 0.11 micron; 0.13 micron; CMOS technology platform; SRAM cell; annealing condition; deep junction activation; disposable gate sidewalls; poly-silicon gate; salicide; second sidewalls; shallow junction formation; source/drain extensions; system on a chip; trench capacitor DRAM cell; Annealing; Boron; CMOS technology; Capacitors; Degradation; Logic; MOSFET circuits; Random access memory; Silicides; Temperature;

fLanguage

English

Publisher

ieee

Conference_Titel

VLSI Technology, 2000. Digest of Technical Papers. 2000 Symposium on

Conference_Location

Honolulu, HI, USA

Print_ISBN

0-7803-6305-1

Type

conf

DOI

10.1109/VLSIT.2000.852802

Filename

852802