DocumentCode
2161995
Title
Initialization issues in the synthesis of asynchronous circuits
Author
Banerjee, Savita ; Roy, Rabindra K. ; Chakradhar, Srimat T. ; Pradhan, Dhiraj K.
Author_Institution
Dept. of Electr. & Comput. Eng., Massachusetts Univ., Amherst, MA, USA
fYear
1994
fDate
10-12 Oct 1994
Firstpage
447
Lastpage
452
Abstract
We present a procedure for synthesizing initializable asynchronous circuits from functionally uninitializable Signal Transition Graphs (STG). After characterizing the necessary conditions for functional uninitializability, we propose a technique that transforms the original STG into an equivalent, functionally initializable STG. It is shown that initializability can be achieved by sacrificing minimal concurrency without violating the syntactic properties of the STG required for a hazard-free implementation. The synthesis of a trigger module illustrates this procedure
Keywords
asynchronous sequential logic; logic CAD; logic testing; sequential circuits; asynchronous circuits; hazard-free implementation; initializable asynchronous circuits; initialization issues; minimal concurrency; necessary conditions; trigger module; uninitializable Signal Transition Graphs; Asynchronous circuits; Automatic test pattern generation; Automatic testing; Circuit synthesis; Circuit testing; Concurrent computing; DH-HEMTs; National electric code; Signal synthesis; Test pattern generators;
fLanguage
English
Publisher
ieee
Conference_Titel
Computer Design: VLSI in Computers and Processors, 1994. ICCD '94. Proceedings., IEEE International Conference on
Conference_Location
Cambridge, MA
Print_ISBN
0-8186-6565-3
Type
conf
DOI
10.1109/ICCD.1994.331947
Filename
331947
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