Title :
The structured logic CAD suite used on the DPS7000 system
Author :
Nguyen, H.N. ; Tual, J.P. ; Ducousso, L. ; Thill, U. ; Vallet, P.
Author_Institution :
Dept. of Des. Methodology, Bull SA, Les Clayes-sous-Bois, France
Abstract :
This paper describes the large scale application of logic synthesis and formal verification to the design of the CPU and cache of the high-end series of the Bull DPS7000 mainframe family. The logic CAD suite used for supporting this application proved its efficiency on the design of high-performance circuits
Keywords :
buffer storage; formal verification; logic CAD; mainframes; Bull DPS7000 mainframe family; CPU design; DPS7000 system; cache; formal verification; high-performance circuit design; large scale application; logic CAD suite; logic synthesis; structured logic CAD suite; CMOS technology; Central Processing Unit; Circuit synthesis; Computational modeling; Design methodology; Formal verification; Hardware; Logic design; Signal synthesis; Very large scale integration;
Conference_Titel :
Computer Design: VLSI in Computers and Processors, 1994. ICCD '94. Proceedings., IEEE International Conference on
Conference_Location :
Cambridge, MA
Print_ISBN :
0-8186-6565-3
DOI :
10.1109/ICCD.1994.331951
