A 0.99-/spl mu/m/sup 2/ loadless four-transistor SRAM cell in 0.13-/spl mu/m generation CMOS technology

Author

Masuoka, S. ; Noda, K. ; Ito, S. ; Matsui, K. ; Imai, K. ; Yasuzato, N. ; Kawamoto, H. ; Ikezawa, N. ; Ando, K. ; Koyama, S. ; Tamura, T. ; Yamada, Y. ; Horiuchi, T.

Author_Institution

ULSI Device Dev. Lab., NEC Corp., Sagamihara, Japan

fYear

2000

fDate

13-15 June 2000

Firstpage

164

Lastpage

165

Abstract

Summary form only given. We present an ultra-high-density embedded loadless four-transistor SRAM cell for 0.13-/spl mu/m logic LSIs. The cell size is 0.99 /spl mu/m/sup 2/, which is the smallest of all reported SRAM cells. In addition, its fabrication process is fully compatible with CMOS logic technologies. The following three technologies reduce the cell area to less than 1 /spl mu/m/sup 2/, and provide highly stable operation at 1.2 V. The double-exposure technique using KrF excimer laser lithography with complementary phase-shift masks reduces the spacing between the drive-transistor gate and the word line. Using the borderless-contact etching process expands shared contact up to 0.21 /spl mu/m without contact leakage current to obtain sufficient misalignment tolerance. The thickness of the gate dielectrics in the cell is controlled to suppress the direct tunneling current to less than the off-state current in order to retain the cell data from -40 to 125/spl deg/C.

Keywords

CMOS logic circuits; CMOS memory circuits; SRAM chips; VLSI; etching; high-speed integrated circuits; integrated circuit technology; large scale integration; photolithography; -40 to 125 C; 0.13 micron; 1.2 V; CMOS technology; KrF; KrF excimer laser lithography; borderless-contact etching process; complementary phase-shift masks; direct tunneling current suppression; double-exposure technique; embedded SRAM cell; fabrication process; gate dielectric thickness control; highly stable operation; loadless four-transistor SRAM cell; logic LSI devices; static RAM; ultra-high-density SRAM cell; CMOS logic circuits; CMOS process; CMOS technology; Dielectrics; Etching; Laser stability; Leakage current; Lithography; Optical device fabrication; Random access memory;

fLanguage

English

Publisher

ieee

Conference_Titel

VLSI Technology, 2000. Digest of Technical Papers. 2000 Symposium on

Conference_Location

Honolulu, HI, USA

Print_ISBN

0-7803-6305-1

Type

conf

DOI

10.1109/VLSIT.2000.852810

Filename

852810