Title :
High-performance 80-nm gate length SOI-CMOS technology with copper and very-low-k interconnects
Author :
Sukegawa, K. ; Yamaji, M. ; Yoshie, K. ; Furumochi, K. ; Maruyama, T. ; Morioka, H. ; Naori, N. ; Kubo, T. ; Kanata, H. ; Kai, M. ; Satoh, S. ; Izawa, T. ; Kubota, K.
Author_Institution :
Fujitsu Ltd., Mie, Japan
Abstract :
High-performance 0.13-/spl mu/m CMOS logic technology has been developed using partially-depleted SOI transistors, EB lithography, and seven-layer copper dual-damascene interconnects with an organic very-low-k dielectric. The technology achieves 9-psec inverter delay at 1.3 V, a 60-m/spl Omega///spl square/ sheet resistance of interconnects, and a 30% smaller intra-layer capacitance than USG. This technology is applied to 1.5-GHz MPU chips.
Keywords :
CMOS logic circuits; capacitance; copper; dielectric thin films; electron beam lithography; integrated circuit interconnections; microprocessor chips; organic compounds; silicon-on-insulator; 0.13 mum; 1.3 V; 1.5 GHz; 80 nm; 9 ps; CMOS logic technology; EB lithography; MPU chips; Si-SiO/sub 2/; copper; high-performance SOI-CMOS technology; intra-layer capacitance; inverter delay; low-k interconnects; organic very-low-k dielectric; partially-depleted SOI transistors; seven-layer copper dual-damascene interconnects; sheet resistance; CMOS technology; Copper; Delay; Dielectrics; Laboratories; Lithography; MOS devices; Silicon on insulator technology; Steady-state; Voltage;
Conference_Titel :
VLSI Technology, 2000. Digest of Technical Papers. 2000 Symposium on
Conference_Location :
Honolulu, HI, USA
Print_ISBN :
0-7803-6305-1
DOI :
10.1109/VLSIT.2000.852819
