Optimal datapath synthesis of partitioned signal processing algorithm for multiple FPGAs

A novel integer linear programming (ILP) formulation for optimally mapping a partitioned signal processing algorithm on a multiple FPGA board is presented. Our approach performs all the following synthesis bindings simultaneously: operation scheduling, function unit allocation, interconnections, data-transfer scheduling between FPGAs, and input/output port allocation. Moreover, we present architectural models suitable for multiple FPGA boards and account for limitations in the structure of interconnections of multiple FPGAs. We demonstrate the quality of the results of our approach for typical signal processing synthesis benchmarks, including the difficult examples of discrete and inverse discrete cosine transforms (DCT and IDCT)