Reducing power dissipation in serially connected MOSFET circuits via transistor reordering

Author

Hossain, Razak ; Zheng, Menghui ; Albicki, Alexander

Author_Institution

Dept. of Electr. Eng., Rochester Univ., NY, USA

fYear

1994

fDate

10-12 Oct 1994

Firstpage

614

Lastpage

617

Abstract

In this paper we show how transistor reordering based on input signal probabilities can substantially reduce the expected dynamic power dissipation in serially connected MOSFETs. The paper includes a new model for the power dissipation in a MOSFET chain and extensive simulation results. Our results indicate that transistor reordering can significantly reduce the power dissipation in CMOS NAND gates

Keywords

circuit analysis computing; field effect transistor circuits; logic gates; MOSFET chain; NAND gates; dynamic power dissipation; input signal probabilities; power dissipation; serially connected MOSFET circuits; simulation; transistor reordering; Analytical models; CMOS technology; Capacitance; Circuit simulation; MOSFET circuits; Power MOSFET; Power dissipation; Power measurement; Semiconductor device modeling; Very large scale integration;

fLanguage

English

Publisher

ieee

Conference_Titel

Computer Design: VLSI in Computers and Processors, 1994. ICCD '94. Proceedings., IEEE International Conference on

Conference_Location

Cambridge, MA

Print_ISBN

0-8186-6565-3

Type

conf

DOI

10.1109/ICCD.1994.331989

Filename

331989

Link To Document

https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=2162872