A high-density and low-cost self-aligned shallow trench isolation NOR flash technology with 0.14/spl mu/m/sup 2/ cell size

Author

Song, Yong ; Han, J.I. ; Kim, Jin W. ; Park, Jae Hyo ; Kim, Soo Youn ; Kwon, D.W. ; Park, Y.M. ; Lee, Joon Sang ; Lee, W.K. ; Lee, Deuk Y. ; Kim, Jin W. ; Kang, M.S. ; Kim, Jung-Ho ; Suh, K.D.

Author_Institution

Memory Div., Samsung Electron. Co., LTD, Kyunggi-Do, South Korea

fYear

2001

fDate

2-5 Dec. 2001

Abstract

We have developed a new cell technology with extremely small cell size of 0.14 /spl mu/m/sup 2/ using 0.12 /spl mu/m process. The self-aligned shallow trench isolation (SA-STI) and self-aligned source (SAS) structure are adopted to minimize the cell size. To scale down the cell gate length and to improve the cell performance, high aspect-ratio floating gate and channel erasing scheme are used. Excellent endurance characteristics, tight threshold voltage distribution and good reliability have been verified in this work.

Keywords

NOR circuits; cellular arrays; flash memories; integrated circuit reliability; isolation technology; 0.12 micron; NOR flash technology; aspect-ratio floating gate; cell size; channel erasing scheme; endurance characteristics; gate length; reliability; self-aligned shallow trench isolation; self-aligned source structure; threshold voltage distribution; Channel hot electron injection; Etching; Flash memory; Flash memory cells; Implants; Isolation technology; Nonvolatile memory; Rails; Synthetic aperture sonar; Threshold voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

Electron Devices Meeting, 2001. IEDM '01. Technical Digest. International

Conference_Location

Washington, DC, USA

Print_ISBN

0-7803-7050-3

Type

conf

DOI

10.1109/IEDM.2001.979397

Filename

979397