Title :
A skew and jitter suppressed DLL architecture for high frequency DDR SDRAMs
Author :
Hamamoto, T. ; Kawasaki, S. ; Furutani, K. ; Yasuda, K. ; Konishi, Y.
Author_Institution :
ULSI Dev. Center, Mitsubishi Electr. Corp., Hyogo, Japan
Abstract :
This paper demonstrates a skew and jitter suppressed delay locked loop (DLL) architecture used for over 400 Mbps operating DDR SDRAMs. Two novel replica adjusting techniques are introduced, which reduce timing skews between external clocks and data outputs. An improved delay line architecture is introduced, which realizes a high frequency and jitter suppressed DLL.
Keywords :
DRAM chips; Delay lines; Delay lock loops; Memory architecture; Timing jitter; 400 Mbit/s; delay line architecture; delay locked loop; double data rate; dynamic RAM; high frequency DDR SDRAMs; jitter suppressed DLL architecture; memory chips; replica adjusting techniques; skew suppressed DLL architecture; synchronous DRAM; timing skews; Circuits; Clocks; DRAM chips; Delay lines; Frequency; Jitter; SDRAM; Timing; Ultra large scale integration; Voltage;
Conference_Titel :
VLSI Circuits, 2000. Digest of Technical Papers. 2000 Symposium on
Conference_Location :
Honolulu, HI, USA
Print_ISBN :
0-7803-6309-4
DOI :
10.1109/VLSIC.2000.852857
