Design impact study of wiring size and barrier metal on device performance toward 22 nm-node featuring EUV lithography

Author

Nakamura, N. ; Takigawa, Y. ; Soda, E. ; Hosoi, N. ; Tarumi, Y. ; Aoyama, H. ; Tanaka, Y. ; Kawamura, D. ; Ogawa, S. ; Oda, N. ; Kondo, S. ; Mori, I. ; Saito, S.

Author_Institution

Semicond. Leading Edge Technol., Inc., Tsukuba

fYear

2009

fDate

1-3 June 2009

Firstpage

14

Lastpage

16

Abstract

The resistance of wiring with a width of less than 40 nm was firstly evaluated by using an EUV lithography (lambda=13.5 nm). The resistance was quite high in narrow wiring with conventional Ta barrier film, while a very low effective resistivity rho_eff of lower than 4.5 muOmega cm was obtained by using PVD-Ru barrier film. This difference was attributed to combination of thinner barrier metal films in the trench, the larger grain size and better filling capability of the Ru barrier metal. The predicted circuit-performance using the Ru barrier was 10% higher than that with Ta barrier and the operating-speed distribution was estimated to be less than 5 % for the 22 nm-node CMOS generation.

Keywords

contact resistance; electrical resistivity; grain size; integrated circuit interconnections; ruthenium; tantalum; ultraviolet lithography; wiring; Cu; EUV lithography; PVD-Ru barrier film; Ru; Ta; barrier metal; effective resistivity; grain size; size 22 nm; wavelength 13.5 nm; wiring resistance; wiring size; Atmosphere; Capacitance; Copper; Etching; Filling; Grain size; Integrated circuit interconnections; Lithography; Resists; Wiring;

fLanguage

English

Publisher

ieee

Conference_Titel

Interconnect Technology Conference, 2009. IITC 2009. IEEE International

Conference_Location

Sapporo, Hokkaido

Print_ISBN

978-1-4244-4492-2

Electronic_ISBN

978-1-4244-4493-9

Type

conf

DOI

10.1109/IITC.2009.5090328

Filename

5090328