TSV-aware interconnect length and power prediction for 3D stacked ICs

In this paper, we present a new 3D wirelength distribution model which considers the contribution of through-silicon-via (TSV) on wirelength, die area, and power consumption. Since TSVs occupy the device layer together with active devices, the die area increases if TSVs are utilized. This area overhead, which in turn affects the wirelength, worsens due to the large size of TSVs themselves, which is shown to be as large as logic gates themselves. Moreover, the capacitive coupling among TSVs and wires cause non-negligible amount of parasitic capacitance, which worsens power consumption. We present and validate a new 3D wirelength distribution and power consumption model to correctly model the various impacts of TSV.