Title :
470 ps 64-bit parallel binary adder [for CPU chip]
Author :
Jaehong Park ; Ngo, H.C. ; Silberman, Joel A. ; Dhong, S.H.
Author_Institution :
Samsung Electron., Kyunggi-Do, South Korea
Abstract :
This paper presents a fast 64-bit parallel carry look-ahead binary adder implemented in a 1 GHz research prototype 64-bit PowerPC microprocessor. Efficient use of dynamic compound gates enables implementation of the adder in just three stages of delayed reset dynamic logic. The computation uses only G (Generate) and P (Propagate), and the inverse of Carry is computed from G, P, and a strobe signal.
Keywords :
Adders; Carry logic; Circuit simulation; Integrated circuit design; Microprocessor chips; Parallel architectures; VLSI; 1 GHz; 470 ps; 64 bit; PowerPC microprocessor; carry look-ahead adder; delayed reset dynamic logic; dynamic compound gates; parallel binary adder; Adders; CMOS technology; Circuit simulation; Circuit synthesis; Computer architecture; DH-HEMTs; Delay; Microprocessors; Prototypes; Signal generators;
Conference_Titel :
VLSI Circuits, 2000. Digest of Technical Papers. 2000 Symposium on
Conference_Location :
Honolulu, HI, USA
Print_ISBN :
0-7803-6309-4
DOI :
10.1109/VLSIC.2000.852887
