DocumentCode :
2164225
Title :
Optimizing constraints for speed: benchmarking temporal logic
Author :
Jakob, J.I.
Author_Institution :
Tech. Univ. Hamburg-Harburg, Germany
fYear :
1994
fDate :
5-9 Sep 1994
Firstpage :
189
Lastpage :
194
Abstract :
The notion of local constraint processors (“constraint chips”) is introduced. Local constraint processors are defined as hardware chips for processing local (discrete-valued and/or continuous-valued) constraints of arbitrary arity (also referred to as a “constraint class”) in a constraint network. A family of constraint chips supporting temporal scheduling and planning tasks (particularly in the manufacturing domain) is presented. One of these chips/constraint classes is selected (qualitative temporal logic) and compared with an efficient software solution of the same constraint class, with the help of a benchmark family derived from the manufacturing domain. The result shows that constraint chips used as coprocessors generally are faster than efficient software solutions of the same constraint class, but critically depend on the quality of hardware integration into a computer system
Keywords :
computer aided production planning; constraint handling; manufacturing data processing; microprocessor chips; temporal logic; temporal reasoning; constraint chips; constraint network; constraint optimisation; local constraint processors; manufacturing scheduling; planning tasks; temporal logic; temporal scheduling;
fLanguage :
English
Publisher :
iet
Conference_Titel :
Intelligent Systems Engineering, 1994., Second International Conference on
Conference_Location :
Hamburg-Harburg
Print_ISBN :
0-85296-621-0
Type :
conf
DOI :
10.1049/cp:19940623
Filename :
332041
Link To Document :
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