Yield enhancement of wafer scale integrated arrays

In an approach proposed by V.P. Kumar et al. (see Proc. IEEE Int. Conf. on Computer-Aided Design, p.226-9, Nov. 1989) for the yield enhancement of programmable gate arrays (PGAs), an initial placement of a circuit is first obtained using a standard technique such as simulated annealing on a defect-free PGA. In the next step this placement is reconfigured so that the circuit is mapped onto the defect-free portion of a defective PGA chip with the same architecture. In the present work, the authors consider the problem of yield enhancement along the same lines as above not only for PGAs but also for wafer-scale-integrated arrays. A heuristic algorithm for reconfiguration based on a graph-theoretic formulation of the problem and a polynomial-time exact algorithm for a special case of the problem are presented. The reconfiguration algorithms are evaluated by comparing the routability and wire length of the reconfigured and initial placements of the circuit