Statistical model for stress-induced leakage current and pre-breakdown current jumps in ultra-thin oxide layers

Author

Degraeve, R. ; Kaczer, B. ; Schuler, F. ; Lorenzini, M. ; Wellekens, D. ; Hendrickx, P. ; Van Houdt, J. ; Haspeslagh, L. ; Tempel, G. ; Groeseneken, G.

Author_Institution

IMEC, Leuven, Belgium

fYear

2001

fDate

2-5 Dec. 2001

Abstract

We present a statistical, unified picture of Stress-Induced Leakage Current (SILC) generation, pre-breakdown current steps and breakdown in 2.4 nm oxide layers during a constant voltage stress. Pre-breakdown current steps were investigated through gate voltage ramp measurements and modeled by means of a percolation model with variable trap-trap distance. During oxide stress, first single-trap conduction paths are formed, followed by two-trap conduction paths which are identified as pre-breakdown current steps in small devices. Finally, a highly conducting path is formed which triggers breakdown.

Keywords

MOSFET; dielectric thin films; interface states; leakage currents; semiconductor device breakdown; semiconductor device models; statistical analysis; 2.4 nm; CMOS process; NMOSFETs; SILC generation; breakdown; constant voltage stress; gate voltage ramp measurements; percolation model; pre-breakdown current jumps; single-trap conduction paths; statistical model; stress-induced leakage current; two-trap conduction paths; ultra-thin oxide layers; variable trap-trap distance; Breakdown voltage; CMOS process; Current measurement; Degradation; Electric breakdown; Lead compounds; Leakage current; MOSFETs; Stress; Voltage measurement;

fLanguage

English

Publisher

ieee

Conference_Titel

Electron Devices Meeting, 2001. IEDM '01. Technical Digest. International

Conference_Location

Washington, DC, USA

Print_ISBN

0-7803-7050-3

Type

conf

DOI

10.1109/IEDM.2001.979447

Filename

979447