DocumentCode
2164789
Title
An 80 MHz digital signal processing multichip module made with the General Electric high density interconnect technology
Author
Gdula, Michael ; Welles, Kenneth B., II ; Wojnarowski, Robert J.
Author_Institution
GE Corp. Res. & Dev. Center, Schenectady, NY, USA
fYear
1991
fDate
29-31 Jan 1991
Firstpage
192
Lastpage
198
Abstract
A unique packaging and interconnect technology was used to build a multichip, four CPU element, pipeline parallel processing computer module using Texas Instruments TMS320C25 digital signal processors and companion circuits. The technology allowed a greater than fifteen-fold reduction in area over conventional chip packages mounted with printed-circuit-board methods. Reduced interconnect capacitance coupled with elimination of conventional package parasitics allowed clocking of commercial 40 MHz parts to nearly 90 MHz
Keywords
CMOS integrated circuits; digital signal processing chips; hybrid integrated circuits; packaging; parallel machines; pipeline processing; 40 to 90 MHz; CMOS; DSP chips; General Electric; HDI; MCM; TMS320C25; clock frequency 90 MHz; digital signal processors; four CPU element; high density interconnect technology; interconnect capacitance reduction; multichip module; package parasitics elimination; pipeline parallel processing computer module; reduction in area; Central Processing Unit; Concurrent computing; Digital signal processing; Digital signal processing chips; Instruments; Integrated circuit interconnections; Multichip modules; Packaging; Parallel processing; Pipelines;
fLanguage
English
Publisher
ieee
Conference_Titel
Wafer Scale Integration, 1991. Proceedings., [3rd] International Conference on
Conference_Location
San Francisco, CA
Print_ISBN
0-8186-9126-3
Type
conf
DOI
10.1109/ICWSI.1991.151715
Filename
151715
Link To Document