HiPAR-DSP: a parallel VLIW RISC processor for real time image processing applications

Derived from a thorough analysis of a wide class of image processing algorithms´ properties, a parallel RISC architecture has been developed. The architecture gains performance from data level parallelism as well as from instruction level parallelism. From the beginning of the concept phase, high-level programming capabilities have been one of the major design goals. Thus, there has been a steady interaction between the design of the software development toolkit-optimizing assembler and C++ compiler-and the architecture itself. The RISC-typical register files are one of the most critical elements as well concerning die size and clock frequency as the assembler´s ability in VLIW scheduling. Running at 100 MHz (200 mm² , 0.35 μm CMOS) the processor reaches a sustained performance of more than 2 GOPS for a wide range of image processing algorithms