Title :
70 nm SOI-CMOS of 135 GHz f/sub max/ with dual offset-implanted source-drain extension structure for RF/analog and logic applications
Author :
Matsumoto, T. ; Maeda, S. ; Ota, K. ; Hirano, Y. ; Eikyu, K. ; Sayama, H. ; Iwamatsu, T. ; Yamamoto, K. ; Katoh, T. ; Yamaguchi, Y. ; Ipposhi, T. ; Oda, H. ; Maegawa, S. ; Inoue, Y. ; Inuishi, M.
Author_Institution :
ULSI Dev. Center, Mitsubishi Electr. Corp., Itami, Japan
Abstract :
We achieved 135 GHz f/sub max/ and 10.98 dB MSG at 40 GHz, which represent the world record data in CMOS published papers, by using a 70 nm body-tied partially-depleted (PD) SOI-CMOS with offset-implanted source-drain extension (SDE) and thick cobalt salicide. The suppression of V/sub th/ variations was also realized due to this structure. Dual offset-implanted SDE structure was proposed to realize high performance of both RF/analog and logic applications. We found that the optimized offset gate spacer width of the RF/analog parts is different from that of the logic parts.
Keywords :
CMOS analogue integrated circuits; CMOS logic circuits; ion implantation; silicon-on-insulator; 10.98 dB; 135 GHz; 70 nm; CoSi/sub 2/-Si; RF/analog applications; body-tied partially-depleted SOI-CMOS; cobalt salicide; dual offset-implanted source-drain extension; logic applications; offset gate spacer; threshold voltage; CMOS logic circuits; Cobalt; Conductivity; Immune system; Large scale integration; Logic devices; MOSFET circuits; Parasitic capacitance; Radio frequency; Ultra large scale integration;
Conference_Titel :
Electron Devices Meeting, 2001. IEDM '01. Technical Digest. International
Conference_Location :
Washington, DC, USA
Print_ISBN :
0-7803-7050-3
DOI :
10.1109/IEDM.2001.979470
