Title :
A 50-nm CMOS technology for high-speed, low-power, and RF applications in 100-nm node SoC platform
Author :
Ohnishi, K. ; Tsuchiya, R. ; Yamauchi, Takashi ; Ootsuka, F. ; Mitsuda, K. ; Hase, M. ; Nakamura, T. ; Kawahara, T. ; Onai, T.
Author_Institution :
Central Res. Lab., Hitachi Ltd., Kokubunji, Japan
Abstract :
We have developed 100-nm node CMOS platform mixed with high performance and low-power/RF applications. This platform is featured by an Offset Source/Drain structure for gate length reduction without reducing drive current, and by a SSC (Super Steep Channel) profile for improving low-power/RF performance in terms of carrier mobility and 1/f noise.
Keywords :
1/f noise; CMOS integrated circuits; carrier mobility; doping profiles; high-speed integrated circuits; integrated circuit noise; integrated circuit technology; low-power electronics; 1/f noise; 100 nm; 50 nm; CMOS technology; RF applications; carrier mobility; drive current; gate length; high-speed applications; low-power applications; offset source/drain structure; super steep channel profile; system-on-a-chip; Application specific integrated circuits; CMOS integrated circuits; CMOS technology; Dielectric devices; Fabrication; Ion implantation; Laboratories; Low voltage; MOSFET circuits; Radio frequency;
Conference_Titel :
Electron Devices Meeting, 2001. IEDM '01. Technical Digest. International
Conference_Location :
Washington, DC, USA
Print_ISBN :
0-7803-7050-3
DOI :
10.1109/IEDM.2001.979472
