Title :
An overview and analysis of 3D WSI
Author_Institution :
Center for Integrated Electron., Rensselaer Polytech. Inst., Troy, NY, USA
Abstract :
The author reviews the early trends in 3-D WSI (wafer scale integration) and examines recent breakthroughs in technology to assess the viability of 3-D. It is concluded that this option is rich with possibility for the designer. However, not every architecture can benefit equally from this packaging approach. An attempt is made to quantify this impact by computing an average wire-shortening effect from 3-D partitioning, but even this average improvement is pessimistic if the given architecture is such that the most critical paths can all be placed on the vertical wiring runs in the stack, depending on the vertical spacing of the wafers
Keywords :
VLSI; hybrid integrated circuits; microprocessor chips; packaging; 3-D partitioning; 3D WSI; WSI stacking; analysis; average wire-shortening effect; breakthroughs in technology; critical paths; overview; vertical spacing; vertical wiring runs; viability of 3-D; wafer scale integration; Delay effects; Dielectric thin films; Frequency; Integrated circuit interconnections; Propagation losses; Skin effect; Transmission lines; Wafer scale integration; Wires; Wiring;
Conference_Titel :
Wafer Scale Integration, 1991. Proceedings., [3rd] International Conference on
Conference_Location :
San Francisco, CA
Print_ISBN :
0-8186-9126-3
DOI :
10.1109/ICWSI.1991.151719
