A 100 nm node CMOS technology for practical SOC application requirement

Reports a 1.0 V operation 100 nm technology node CMOS technology for generic SOC application. We have estimated that for practical SOC chip/package design, target spec of both I/sub OFF/ and I/sub G/ must be below 5 nA//spl mu/m in view of heat generation issue. The key point is how to obtain higher drive current under this I/sub OFF//I/sub G/ restriction. Taking this criteria into account, we optimized 1) the gate dielectric formation sequence consisting of RTH treatment and radical nitridation; 2) gate off-set spacer optimization for practical and robust 100 nm-node CMOS technology. Fabricated transistor, featuring 65 nm gate length and 1.6nm-EOT gate dielectric, show 640/260 /spl mu/A//spl mu/m of I/sub ON/ and 5n/5n A//spl mu/m of I/sub OFF/ with 1.0V operation.