DocumentCode
2167058
Title
Modeling and Simulation of Circuit Aging in Scaled CMOS Design
Author
Yu Kao
Author_Institution
Arizona State Univ., Phoenix, AZ
fYear
2008
fDate
7-9 July 2008
Firstpage
197
Lastpage
197
Abstract
The document was not made available for publication as part of the conference proceedings.
Keywords
CMOS integrated circuits; ageing; integrated circuit design; integrated circuit modelling; semiconductor process modelling; circuit aging; circuit modeling; circuit simulation; scaled CMOS design; Aging; Circuit simulation; Circuit testing; Semiconductor device modeling;
fLanguage
English
Publisher
ieee
Conference_Titel
On-Line Testing Symposium, 2008. IOLTS '08. 14th IEEE International
Conference_Location
Rhodes
Print_ISBN
978-0-7695-3264-6
Type
conf
DOI
10.1109/IOLTS.2008.65
Filename
4567094
Link To Document