Guided Probabilistic Checksums for Error Control in Low Power Digital-Filters

In many DSP applications (image and voice processing, baseband symbol decoding in high quality communication channels) several dBs of SNR loss can be tolerated without noticeable impact on system level performance. For power optimization in such applications, voltage overscaling can be used to operate the arithmetic circuitry slower than the critical circuit path delay while incurring tolerable SNR loss due to the resulting periodic errors in computation. In this paper, the use of checksum codes along with low precision shadow latches for compensating errors induced by voltage overscaling in digital filters is investigated. A PID controller is used for voltage overscaling while keeping the error rate in the system within acceptable range. It is shown that significant power savings can be achieved by the proposed technique.