A DFT Loopback Scheme for ADC ENOB Testing Using an All-Digital ATE

This article presents a design-for-test (DFT) loopback scheme for testing the analog portion of a mixed-signal chip using an all- digital tester. In fact, the proposed approach is used to assess the ENOB of a high-speed 6-bit ADC without the need for an external signal generator. Using an on-chip PLL with a programmable divider, a divided version of the 16GHz clock is passed through an on-chip buffer network where the output driver amplitude is programmable to achieve the desired fill ratio (~80%). The test PLL is coherent to the system PLL as they are driven from the same reference clock; hence, no windowing needs to be applied to the ADC output prior to performing the FFT for ENOB assessment. The on-chip output driver has an open-drain configuration that is far- end terminated through 50Ω pull-up resistors connected to a 2.0V external supply on the device interface board (DIB). The output is then applied to a 5th order external filter on the DIB with a 3dB cutoff frequency of 2.4GHz to filter out the high order harmonics prior to looping back the stimulus to the ADC front-end. The proposed scheme is implemented within a CMOS 32nm ADC macro and is experimentally validated using a commercial all-digital automated-test-equipment (ATE). A 4.5 bit ENOB was experimentally measured using the ADC under test. Unlike conventional loopback schemes, the proposed architecture is not susceptible to fault masking.