A broadband FFT processor core based on FPGA

This paper presents an implementation of a real-time FFT processor based on FPGA, which uses the radix-4 DIF (decimation-in-frequency) algorithm. Five stages of radix-4 butterflies are used to make up of a pipeline to compute the 1024-point complex FFT. The FFT processor can operate at 164 MHz and compute a 1024-point FFT at 6.225 mus when operating on the device of Xilinx Virtex II Pro 70. This will accommodate a high data throughput transmitted to the back end instrument.