Study of a new structured leadframe based CSP, Mini-LOC

A new CSP (chip scale package) package named Mini-LOC (lead on chip), mainly applied on DRAM, is developed by SPIL to offer a leadframe based CSP package with lower cost, enhanced thermal and electrical performance solution for assembly industries. Solder mask is printed on special designed non-outer lead leadframe to define pad openings for ball connections to shrink the package´s size and improve its thermal and electrical performance. Finite element analysis is employed to characterize thermal, electrical performance of Mini-LOC package. A traditional TSOP-LOC package with similar I/O is also analyzed and compared to study the advantages of this new structured package. The results indicate the enhanced electrical characteristics with 61% decrease in mutual-inductance and 42% decrease in mutual-capacitance as well as the thermal performance of 35% decrease in Theta Ja (C/W) compared with those of the conventional TSOP-LOC package