DocumentCode :
2167891
Title :
Best Practices for System Level ESD Testing of Semiconductor Components
Author :
Muhonen, Kathleen
Author_Institution :
RFMD, Greensboro, NC, USA
fYear :
2013
fDate :
13-16 Oct. 2013
Firstpage :
1
Lastpage :
4
Abstract :
Electrostatic discharge (ESD) testing of integrated circuits (ICs) is necessary to ensure products can withstand several types of ESD threats including those encountered in the factory and in the field. This paper discusses the testing of components with electrostatic stress waveforms that were originally designed for predicting system failures in the field. IC manufacturers are struggling to obtain reliable data when applying system tests to their components because of interface, implementation and equipment repeatability problems found with this form of evaluation. This paper highlights the best practices for system level ESD testing despite these hurdles.
Keywords :
electrostatic discharge; integrated circuit reliability; integrated circuit testing; ESD threats; IC manufacturers; electrostatic discharge testing; electrostatic stress waveforms; equipment repeatability problems; integrated circuits; semiconductor components; system level ESD testing; Electrostatic discharges; Hidden Markov models; IEC standards; Resistance; Strips; Testing; Weapons;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Compound Semiconductor Integrated Circuit Symposium (CSICS), 2013 IEEE
Conference_Location :
Monterey, CA
Type :
conf
DOI :
10.1109/CSICS.2013.6659220
Filename :
6659220
Link To Document :
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