Prototype hardware implementation of a single-chip multiprocessor with a split-transaction bus

This paper presents the results for a prototype hardware implementation in programmable logic of a single-chip cache-coherent multiprocessor based on a split-transaction bus. This implementation provides the basis for further research prototyping to investigate architectures and applications for processor-memory integration. A 4-processor system synthesized for a Xilinx XCV2000E chip consumes only 62% of the available logic resources. Operational results for the implementation collected with a logic analyzer highlight the support for multiple concurrent requests and other features of the split-transaction bus in a multiprocessor.