DocumentCode :
2169889
Title :
A 185 GHz f/sub max/ SOI DTMOS with a new metallic overlay-gate for low-power RF applications
Author :
Hirose, T. ; Momiyama, Y. ; Kosugi, M. ; Kano, H. ; Watanabe, Y. ; Sugii, T.
Author_Institution :
Fujitsu Labs. Ltd., Atsugi, Japan
fYear :
2001
fDate :
2-5 Dec. 2001
Abstract :
The dynamic threshold MOS transistor (DTMOS) built on an SOI substrate is one candidate to realize low-power one-chip RF and high-speed digital integrated circuits for wireless communication systems and optical fiber links. Scaling down the characteristic length of the DTMOS is aggressively performed, and the cut-off frequency (f/sub T/) has been drastically increased. Although the f/sub T/ is steeply rising every year, improvement of the maximum oscillation frequency (f/sub max/) is very slow. This is due to a limitation of the silicide based gate resistance (Rg) in the conventional logic CMOS process. Many interesting ways with optimized layout such as folded gate finger and multi-finger pattern have been proposed, and great efforts to make Rg small have been made. The most effective way to perform further reduction of Rg is to use a low resistive metal-gate or a metallic overlay-gate that is fabricated on the poly-Si fine gate. In this paper, we propose an 80 nm gate SOI-nDTMOS with a new gate structure. The key is to introduce a metallic overlay-gate process into the conventional logic CMOS fabrication process. Using the metallic overlay-gate structure, we achieved the f/sub max/ of 185 GHz at low bias voltage, which is, in our knowledge, the world record ever reported for Si MOSFETs.
Keywords :
MOS integrated circuits; MOSFET; UHF field effect transistors; UHF integrated circuits; field effect MIMIC; field effect MMIC; high-speed integrated circuits; integrated circuit metallisation; low-power electronics; microwave field effect transistors; millimetre wave field effect transistors; semiconductor device metallisation; silicon-on-insulator; 185 GHz; 80 nm; MOS transistor; RF integrated circuits; RF/digital ICs; RFICs; SOI DTMOS; SOI substrate; Si; characteristic length scaling; dynamic threshold MOS; gate resistance; high-speed ICs; low-power RF applications; maximum oscillation frequency; metallic overlay-gate process; poly-Si fine gate; CMOS logic circuits; CMOS process; Cutoff frequency; Digital integrated circuits; MOSFETs; Optical fibers; Radio frequency; Roentgenium; Silicides; Wireless communication;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Electron Devices Meeting, 2001. IEDM '01. Technical Digest. International
Conference_Location :
Washington, DC, USA
Print_ISBN :
0-7803-7050-3
Type :
conf
DOI :
10.1109/IEDM.2001.979672
Filename :
979672
Link To Document :
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