Title :
An Efficient Algorithm for Finding a Universal Set of Testable Long Paths
Author :
He, Zijian ; Lv, Tao ; Li, Huawei ; Li, Xiaowei
Author_Institution :
Key Lab. of Comput. Syst. & Archit., Inst. of Comput. Technol. Chinese Acad. of Sci., Beijing, China
Abstract :
In this paper, we focus on generation of a universal path candidate set U that contains testable long paths for delay testing. Some strategies are presented to speed up the depth first search procedure of U generation, targeting the reduction of sensitization criteria checking times. Experimental results illustrate that our approach achieves an 8X speedup on average in comparison with the traditional depth first search approach.
Keywords :
circuit testing; delays; logic circuits; delay testing; testable long path universal set; Algorithm design and analysis; Automatic test pattern generation; Correlation; Delay; Logic gates; Upper bound; delay testing; testable long paths;
Conference_Titel :
Test Symposium (ATS), 2010 19th IEEE Asian
Conference_Location :
Shanghai
Print_ISBN :
978-1-4244-8841-4
DOI :
10.1109/ATS.2010.61