DocumentCode :
2170117
Title :
Performance analysis for a cache system with different DRAM designs
Author :
Mekhiel, Nagi N. ; McCrackin, Daniel C.
Author_Institution :
Dept. of Electr. Eng., Ryerson Polytech. Inst., Toronto, Ont., Canada
fYear :
1993
fDate :
14-17 Sep 1993
Firstpage :
365
Abstract :
In this article the ATUM traces are used to study cache system performance with different DRAM designs. The performance of the write back and the write through caches with different cache size and set associativity is discussed. The effect of the DRAM fast page mode and the precharge mode on the overall system performance has been presented. The results show that the cache systems that use DRAM with fast page or precharge design can outperform other systems that use normal DRAM design even with a 2 to 4 times larger cache size. Furthermore, the use of fast page and precharge design helps the fast cache much more than the slow cache
Keywords :
buffer storage; performance evaluation; random-access storage; ATUM traces; DRAM designs; cache system; cache system performance; performance analysis; system performance; Clocks; Costs; Delay; Flowcharts; Information retrieval; Interleaved codes; Performance analysis; Prefetching; Random access memory; System performance;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Electrical and Computer Engineering, 1993. Canadian Conference on
Conference_Location :
Vancouver, BC
Print_ISBN :
0-7803-2416-1
Type :
conf
DOI :
10.1109/CCECE.1993.332332
Filename :
332332
Link To Document :
بازگشت