A 3-tier, 3-D FD-SOI SRAM macro

Author

Zia, Aamir ; Jacob, Philip ; Kraft, Russell P. ; McDonald, John F.

Author_Institution

Center for Integrated Electron., Rensselaer Polytech. Inst., Troy, NY

fYear

2008

fDate

2-4 June 2008

Firstpage

277

Lastpage

280

Abstract

Three dimensional memory systems has been argued as a potential pathway in solving the ever growing difference between comparative speeds of CPU and memory systems. In this paper, we describe a three-tier, three-dimensional SRAM macro that has been designed and fabricated in a 0.18 um FD-SOI CMOS technology. 3D stacking is found to improve wire latency as compared to planar memory structure although the reduction is not enough to have a significant effect on access time of the memory. It is argued that the major performance benefit obtained by 3D integration is in term of very wide data bus that can be realized much more easily with 3D structures as compared to 2D memories.

Keywords

SRAM chips; 3D FD-SOI SRAM macro; 3D stacking; FD-SOI CMOS technology; planar memory structure; three dimensional memory systems; three-tier SRAM macro; wire latency; CMOS technology; Clocks; Decoding; Delay effects; Etching; Integrated circuit interconnections; Random access memory; Reduced instruction set computing; Three-dimensional integrated circuits; Wafer bonding;

fLanguage

English

Publisher

ieee

Conference_Titel

Integrated Circuit Design and Technology and Tutorial, 2008. ICICDT 2008. IEEE International Conference on

Conference_Location

Austin, TX

Print_ISBN

978-1-4244-1810-7

Electronic_ISBN

978-1-4244-1811-4

Type

conf

DOI

10.1109/ICICDT.2008.4567295

Filename

4567295