3D CMOS integration: Introduction of dynamic coupling and application to compact and robust 4T SRAM

Author

Batude, P. ; Jaud, M.-A. ; Thomas, O. ; Clavelier, L. ; Pouydebasque, A. ; Vinet, M. ; Deleonibus, S. ; Amara, A.

Author_Institution

CEA/LETI-MINATEC, Grenoble

fYear

2008

fDate

2-4 June 2008

Firstpage

281

Lastpage

284

Abstract

This paper presents an innovative structure based on 3 dimensional integration technology, where ultra thin inter layer dielectric enables a dynamic threshold voltage (V_TH) control. A sequential process flow is proposed to fabricate 3D devices with dynamically tunable V_TH. This ability can be exploited to design SRAMs cells with increased stability and surface density compared to planar technology. Promising results in term of density and stability using TCAD simulations are shown for a 4T SRAM load-less cell.

Keywords

CMOS memory circuits; SRAM chips; 3D CMOS integration; dynamic coupling; dynamic threshold voltage control; robust 4T SRAM; sequential process flow; ultra thin inter layer dielectric; CMOS technology; Dielectric substrates; MOSFETs; Random access memory; Robustness; Silicides; Stability; Temperature sensors; Threshold voltage; Voltage control; 3D IC; Dynamic threshold voltage modification; SRAM; Sequential three dimensional integration;

fLanguage

English

Publisher

ieee

Conference_Titel

Integrated Circuit Design and Technology and Tutorial, 2008. ICICDT 2008. IEEE International Conference on

Conference_Location

Austin, TX

Print_ISBN

978-1-4244-1810-7

Electronic_ISBN

978-1-4244-1811-4

Type

conf

DOI

10.1109/ICICDT.2008.4567296

Filename

4567296