• DocumentCode
    2170498
  • Title

    Timing optimization on mapped circuits

  • Author

    Yoshikawa, Ko ; Ichiryu, Hiroshi ; Tanishita, Hisato ; Suzuki, Sigenobu ; Nornizu, N. ; Kondoh, Akira

  • Author_Institution
    NEC Corporation
  • fYear
    1991
  • fDate
    21-21 June 1991
  • Firstpage
    112
  • Lastpage
    117
  • Keywords
    BiCMOS integrated circuits; Delay effects; Design optimization; Heuristic algorithms; National electric code; Partitioning algorithms; Permission; Signal mapping; Timing; Tree data structures;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Design Automation Conference, 1991. 28th ACM/IEEE
  • Conference_Location
    IEEE
  • Print_ISBN
    0-89791-395-7
  • Type

    conf

  • Filename
    979698
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=2170498