DocumentCode
2170804
Title
Yield & Reliability challenges of BEOL Interconnects
Author
Tan, J.B. ; Zhang, B.C. ; Tang, T.J. ; Perera, C. ; Lim, Y.K. ; Siew, Y.K. ; Ee, Y.C. ; Lu, W. ; Liu, H. ; Seet, C.S. ; Zhang, H. ; Lim, S.K. ; Chua, S.T. ; Ismail, Z. ; Seah, B.M. ; Ee, P.Y. ; Vigar, D. ; Hsia, L.C.
Author_Institution
Chartered Semicond. Manuf. Ltd.
fYear
2006
fDate
5-7 June 2006
Firstpage
6
Lastpage
8
Abstract
This paper analyses a few key yield and reliability challenges of the back-end-of-line (BEOL) interconnects. A discussion of the failure modes and mechanisms are elaborated on challenges arising from weak patterning, missing trench and plasma charging effect. Enhancement of via and bond pad reliability are also discussed
Keywords
failure analysis; integrated circuit interconnections; integrated circuit reliability; integrated circuit yield; back-end-of-line interconnects; bond pad reliability; failure modes; interconnect yield; missing trench; plasma charging effect; via reliability; weak patterning; Bonding; Copper; Etching; Manufacturing industries; Merging; Packaging; Plasma applications; Pulp manufacturing; Resists; Semiconductor device manufacture;
fLanguage
English
Publisher
ieee
Conference_Titel
Interconnect Technology Conference, 2006 International
Conference_Location
Burlingame, CA
Print_ISBN
1-4244-0104-6
Type
conf
DOI
10.1109/IITC.2006.1648630
Filename
1648630
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