Author :
McGahay, V. ; Bonilla, G. ; Chen, F. ; Christiansen, C. ; Cohen, S. ; Cullinan-Scholl, M. ; Demarest, J. ; Dunn, D. ; Engel, B. ; Fitzsimmons, J. ; Gill, J. ; Grunow, S. ; Herbst, B. ; Hichri, H. ; Ida, K. ; Klymko, N. ; Kiene, M. ; Labelle, C. ; Lee, T.
Author_Institution :
IBM Semicond. Res. & Dev. Center, IBM Corp., Hopewell Junction, NY
Abstract :
A low tensile stress SiCOH dielectric with K=2.15 has been developed for implementation in the 2times and 4times fatwire levels for enhanced RC performance in the 65nm technology node. Integration challenges related to mechanical integrity and process-induced damage were successfully overcome. Yield and interconnect reliability metrics comparable to dense K=3 SiCOH have been achieved. Package deep thermal cycle showed sensitivity to assembly which is controllable though chip edge structural engineering
Keywords :
copper; dielectric materials; integrated circuit interconnections; integrated circuit packaging; integrated circuit reliability; integrated circuit yield; silicon compounds; 65 nm; Cu; RC performance; SiCOH; chip edge structural engineering; dielectric material; fatwire levels; interconnect reliability metrics; mechanical integrity; package deep thermal cycle; process-induced damage; tensile stress; yield metrics; Assembly; Dielectric materials; Electronic components; Electronic packaging thermal management; Optical films; Research and development; Semiconductor device manufacture; Semiconductor device packaging; Tensile stress; Thermal engineering;
