• DocumentCode
    2171600
  • Title

    Efficacy of body ties under dynamic switching conditions in partially depleted SOI CMOS technology

  • Author

    Krishnan, Srinath

  • Author_Institution
    Sematech/AMD, Austin, TX, USA
  • fYear
    1997
  • fDate
    6-9 Oct 1997
  • Firstpage
    140
  • Lastpage
    141
  • Abstract
    Historically, body ties have been designed using removal of DC floating-body (FB) effects (e.g., kink, breakdown voltage) as the main criteria. It has been implicitly assumed that the transient FB effects would be minimized too with such a tie. However, such body ties while “suppressing” DC effects, may not necessarily be effective in AC/transient conditions, since the body (dis)charging time constants may be much larger than desired. For example, in a digital SOI CMOS circuit, with the gate switching at a few tens of ps, the efficacy of the body tie may be little or none at all, depending on the response time τB(=RBCB) of the body. Hence, in order to design effective body ties in transients, dynamic (dis)charging effects due to RB and CB in the body must be included
  • Keywords
    CMOS digital integrated circuits; silicon-on-insulator; transient analysis; body ties; digital circuit; dynamic switching; partially depleted SOI CMOS technology; transient floating-body effects; Board of Directors; CMOS digital integrated circuits; CMOS technology; DC generators; Equivalent circuits; Hysteresis; Immune system; Switching circuits; Thermal resistance; Voltage;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    SOI Conference, 1997. Proceedings., 1997 IEEE International
  • Conference_Location
    Fish Camp, CA
  • ISSN
    1078-621X
  • Print_ISBN
    0-7803-3938-X
  • Type

    conf

  • DOI
    10.1109/SOI.1997.634972
  • Filename
    634972