A high speed offset-compensated differential comparator in floating body CMOS SOS technology for radiation hard switched-capacitor systems

Author

Edwards, C.F. ; Redman-White, W. ; Bracey, M.

Author_Institution

Dept. of Electron. & Comput. Sci., Southampton Univ., UK

fYear

1997

fDate

6-9 Oct 1997

Firstpage

160

Lastpage

161

Abstract

In this paper we describe how a high performance analogue cell has been designed and simulated using a SOS SPICE model, and successfully fabricated in a 1.5 μm floating body SOS technology. The cell described here is a clocked comparator; this is a fundamental building block for realising high performance analogue-to-digital conversion in any technology. To achieve high tolerance to floating body effects, as well as radiation-induced bias and offset degradation, it is necessary to adopt highly specific design techniques to ensure performance is delivered

Keywords

CMOS analogue integrated circuits; SPICE; comparators (circuits); radiation hardening (electronics); silicon-on-insulator; switched capacitor networks; 1.5 micron; SPICE model; analogue cell; analogue-to-digital conversion; circuit design; fabrication; floating body CMOS SOS technology; high speed offset-compensated differential comparator; radiation hard switched-capacitor system; simulation; CMOS analog integrated circuits; CMOS technology; Capacitors; Circuit synthesis; Diodes; Frequency; Isolation technology; Latches; SPICE; Voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

SOI Conference, 1997. Proceedings., 1997 IEEE International

Conference_Location

Fish Camp, CA

ISSN

1078-621X

Print_ISBN

0-7803-3938-X

Type

conf

DOI

10.1109/SOI.1997.634982

Filename

634982