Optimized S-box design AES core

This paper proposes an efficient solution to combine Rijndael encryption and decryption with on fly Key Scheduler in one FPGA design, with a strong focus on low area constraints and high throughput. In this paper, we investigate a new compact digital hardware implementation of AES Structure with integrated Sub byte and Inverse Sub byte transformation which minimizes the computation cost of the relevant arithmetic in the finite field GF (28), including the cost of the mapping. This approach has advantages over a straightforward implementation using read-only memories for table lookups. The Hardware implementation is compared with the previous work done in this area. The resulting S-box design with subfield operations in GF ((2²)²)² offers a reduction in the reconfigurable logic by 81% low gate count as compared to look up table and 23% better performance in area and faster by 3% in comparison with one using GF ((2⁴)²). Derived architectures are evaluated using popular low-cost field-programmable gate arrays. Using the proposed architecture, a fully sub-pipelined AES core with both inner and outer round pipelining and 7 sub-stages in each round unit implemented using XC2V3000 Virtex -E devices can achieve a throughput of 33.47Gbps at 261.68 MHz and 12542 CLB Slices in non-feedback modes, suitable for high speed applications. Result is compared with the fastest previous FPGA implementation known to date.