A Novel 900 MHz I x V CMOS Multiplier

In this paper a current × voltage multiplier with the FVFCS is presented. This multiplier takes advantage of the very low-impedance input node of the FVFCS to sense the current signals. Additionally, uses a two cross-coupled differential pairs in order to cancel undesired components in the output current. The simulations are carried out using the standard Mixed and RF 180 nm UMC CMOS process and is compared with a previous reported multiplier. The presented multiplier has a bandwidth of 900 MHz with a quiescent current of 203 μA.