DocumentCode
2175160
Title
300 KG gate-array LSI using 0.25-μm ultra-thin-film fully-depleted CMOS/SIMOX with tungsten-deposited source/drain
Author
Sato, Yasuhiro ; Kado, Yuichi ; Tsuchiya, Toshiaki ; Kosugi, Toshihiko ; Ishii, Hiromu ; Nishimura, Kosuke
Author_Institution
NTT Syst. Electron. Labs., Kanagawa, Japan
fYear
1997
fDate
6-9 Oct 1997
Firstpage
168
Lastpage
169
Abstract
Summary form only given. We fabricated a 300 kG gate-array LSI using 0.25 μm ultra-thin-film fully-depleted (FD) CMOS/SIMOX technology with tungsten selective CVD (W-SCVD) to reduce S/D sheet resistance. The usefulness of this technology was confirmed by the fully-functional operation of the LSIs consisting of basic cells with a single diagonal contact
Keywords
CMOS logic circuits; SIMOX; chemical vapour deposition; integrated circuit metallisation; large scale integration; logic arrays; tungsten; 0.25 micron; S/D sheet resistance reduction; Si; W; W selective CVD; W-deposited source/drain; fully-depleted CMOS/SIMOX; gate-array LSI; ultra-thin-film CMOS/SIMOX; CMOS technology; Circuits; Fabrication; Immune system; Inverters; Laboratories; Large scale integration; Plasma devices; Transistors; Tungsten;
fLanguage
English
Publisher
ieee
Conference_Titel
SOI Conference, 1997. Proceedings., 1997 IEEE International
Conference_Location
Fish Camp, CA
ISSN
1078-621X
Print_ISBN
0-7803-3938-X
Type
conf
DOI
10.1109/SOI.1997.634986
Filename
634986
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