Title :
An effective BIST scheme for delay testing
Author :
Li, Xiaowei ; Cheung, Paul Y S
Author_Institution :
Dept. of Electr. & Electron. Eng., Hong Kong Univ., Hong Kong
fDate :
31 May-3 Jun 1998
Abstract :
This paper presents a BIST scheme for the detection of path delay faults. It differs from the traditional BIST schemes which are aimed at stuck-at faults by offering the higher capability of two-pattern generation. The TPG scheme produces test sequences having exactly the same robust path delay fault coverage as single-input-change test sequences. By determining nonadjacent inputs, the reduction of both test length and area overhead can be achieved. Signature analysis under path delay fault conditions is also discussed. Based on true-value simulation, error patterns under the path delay fault model were obtained and were used in aliasing estimation
Keywords :
VLSI; built-in self test; delays; digital integrated circuits; fault diagnosis; integrated circuit testing; logic testing; sequences; BIST scheme; aliasing estimation; area overhead reduction; delay testing; error patterns; path delay fault model; path delay faults; signature analysis; test length reduction; test sequences; true-value simulation; two-pattern generation; Built-in self-test; Circuit faults; Circuit testing; Delay effects; Delay estimation; Electrical fault detection; Fault detection; Logic testing; Robustness; Silicon carbide;
Conference_Titel :
Circuits and Systems, 1998. ISCAS '98. Proceedings of the 1998 IEEE International Symposium on
Conference_Location :
Monterey, CA
Print_ISBN :
0-7803-4455-3
DOI :
10.1109/ISCAS.1998.706913
