DocumentCode :
2175319
Title :
Design optimizations to improve placeability of partial reconfiguration modules
Author :
Koester, Markus ; Luk, Wayne ; Hagemeyer, Jens ; Porrmann, Mario
Author_Institution :
Dept. of Comput., Imperial Coll. London, London
fYear :
2009
fDate :
20-24 April 2009
Firstpage :
976
Lastpage :
981
Abstract :
In partially reconfigurable architectures, system components can be dynamically loaded and unloaded allowing resources to be shared over time. This paper focuses on the relation between the design options of partial reconfiguration modules and their placement at run-time. For a set of dynamic system components, we propose a design method that optimizes the feasible positions of the resulting partial reconfiguration modules to minimize position overlaps. We introduce the concept of subregions, which guarantees the parallel execution of a certain number of partial reconfiguration modules for tiled reconfigurable systems. Experimental results, which are based on a Xilinx Virtex-4 implementation, show that at run-time the average number of available positions can be increased up to 6.4 times and the number of placement violations can be reduced up to 60.6%.
Keywords :
field programmable gate arrays; parallel architectures; reconfigurable architectures; Xilinx Virtex-4 implementation; dynamic system components; parallel execution; partially reconfigurable architectures; system components; Circuits; Design methodology; Design optimization; Educational institutions; Field programmable gate arrays; Hardware; Reconfigurable architectures; Runtime; Tiles; Time sharing computer systems;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Design, Automation & Test in Europe Conference & Exhibition, 2009. DATE '09.
Conference_Location :
Nice
ISSN :
1530-1591
Print_ISBN :
978-1-4244-3781-8
Type :
conf
DOI :
10.1109/DATE.2009.5090806
Filename :
5090806
Link To Document :
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