64 Mbit SOI-DRAM technologies using body-contacted (BC) structure

Author

Koh, Yo-Hwan ; Choi, Jin-Hyeok ; Yang, Ji-Woon ; Nam, Myung-Hee ; Lee, Won-Chang ; Lee, Jong-Wook ; Oh, Min-Rok

Author_Institution

Adv. Device Dept., Hyundai Electron. Ind. Co. Ltd., Kyoungki, South Korea

fYear

1997

fDate

6-9 Oct 1997

Firstpage

170

Lastpage

171

Abstract

Summary form only given. Recently, DRAMs using SOI substrates have been widely needed because of their inherent high speed low power characteristics due to small junction capacitances. However, the floating body effect is the most serious problem. The floating body can cause dynamic retention time problems in DRAMs, and a leakage problem due to a small drain-to-source breakdown voltage. In this work, a Body-Contacted (BC) SOI MOSFET structure with no floating body effect is successfully applied to a 64M SOI DRAM. The layout, process steps and the operation voltage are completely compatible with the bulk MOSFET process. We evaluated the transistor characteristics and the chip performances

Keywords

CMOS memory circuits; DRAM chips; MOSFET; capacitance; electrostatic discharge; integrated circuit technology; leakage currents; silicon-on-insulator; 64 Mbit; ESD; SOI DRAM technologies; SOI MOSFET structure; SOI substrates; Si; body-contacted structure; drain-to-source breakdown voltage; dynamic RAM; dynamic retention time; floating body effect; high speed low power characteristics; junction capacitance; leakage problem; CMOSFETs; Capacitance measurement; Delay effects; MOSFET circuits; Random access memory; Research and development; Semiconductor films; Silicon; Substrates; Voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

SOI Conference, 1997. Proceedings., 1997 IEEE International

Conference_Location

Fish Camp, CA

ISSN

1078-621X

Print_ISBN

0-7803-3938-X

Type

conf

DOI

10.1109/SOI.1997.634987

Filename

634987